In order to build faster and more complex memory devices, device manufacturers have increased the memory capacity of the devices, while reducing the overall size of memory circuits. The desire to increase the operating speed of memory circuits has led to the fabrication of transistors having exceedingly small gate lengths. For example, transistors in non-volatile memory devices are typically fabricated having gate lengths on the order of 0.2 microns and smaller. In addition to fabricating transistors having very small gate, various materials, such as refractory metal silicides, are employed to reduce the electrical resistance within the transistors.
While the use of various refractory metals and refractory metal silicides has led to transistors showing improved performance, further performance increases are possible through the creation of localized strain in the transistor channel region. Strain in the channel region improves the electron mobility and increases the operating speed of N-channel metal-oxide-semiconductor (MOS) transistors. Various techniques are known for creating localized strain in the channel region. For example, providing material interfaces having a lattice mismatch creates biaxial strain that improves both electron and whole mobility. Additionally, strain can be created by forming silicon nitrite layers over the channel region. Further, strain in the channel region can be created by implanting arsenic into a polycrystalline silicon gate electrode, followed by an annealing process to expand the implanted polycrystalline silicon. The annealing process is carried out after forming a thick silicon dioxide layer over the implanted gate electrode. By covering the gate electrode with silicon dioxide, the strain caused by expansion of the polycrystalline silicon is directed to the channel region underlying the gate electrode.
While several techniques exist for creating localized strain in transistor channel regions, the implementation of these techniques in an EEPROM device is problematic. To effectively store data in an EEPROM device, electrical charge must remain on a floating-gate electrode after a programming operation. Programming and erasing operations are carried out at relatively high voltage levels. During high voltage operation, there is a tendency for the charge on the floating-gate electrode to bleed off, or leak, as a result of exposure to high electric fields. When charge leaks from the floating-gate electrode, the memory cell will lose its stored data. Good data retention is a key reliability characteristic of a non-volatile memory device. Although it is desirable to increase the operating speed of EEPROM devices, the techniques for creating localized strain in a transistor channel region described above are largely incompatible with the need for good data retention in the memory device. For example, it is known that poor data retention can occur if the doped passivation layers overlying the floating-gate electrode are separated from the floating-gate electrode by thick intervening dielectric layers. Accordingly, the creation of a strained channel region through the placement of compressive stress on a transistor gate electrode must be undertaken with great care.
Typical EEPROM memory cells include MOS transistors that enable charge to be placed on the floating-gate electrode. Enhanced overall memory device performance can be obtained by increasing the performance of the MOS transistors. Since further scaling of device dimensions to smaller and smaller feature sizes can only be obtained at great expense, creating localized strain in the channel regions of the MOS transistors offers a useful method to increase device performance at minimal expense. The creation of compressive stress in the MOS transistor gate electrodes must, however, be implemented in such a way as to avoid a loss of data retention in an EEPROM device.